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BIOS setup - прошивка, настройка, обновления - описание.

Bios settings

DRAM Idle Timer

HDD S.M.A.R.T Capability

Host Bus Fast Data Ready

IRQ n Used By ISA

ISA MEM Block BASE

OS/2 Onboard Memory > 64MB

Onboard PCI IDE Enable

PCI IDE IRQ Map to

PNP OS Installed

PS/2 Mouse Function Control

Parallel Port Mode (ECP+EPP)

Resources Controlled By

SDRAM Banks Close Policy

SDRAM (CAS Lat/RAS-to-CAS )

SDRAM CAS# Latency

SDRAM CAS to RAS Delay

SDRAM RAS Precharge Time

Speculative Leadoff

Turn-Around Insertion

Video Memory Cache Mode

16 Bit ISA I/O Command WS

16 Bit ISA Mem Command WS

ACPI Suspend Type

AC PWR Loss Restart

Above 1 MB Memory Test

Арбитраж, Bus-Master

Auto Configuration

Auto Detect DIMM/PCI Clk

Boot From LAN First

Boot Up Floppy Seek

Boot Up Numlock Status

Boot Up System Speed

Boot Virus Detection

CPU Critical Temperature

CPU External Cache

CPU Fast String

CPU Internal Cache

CPU Level 1 Cache

CPU Level 2 Cache

CPU Level 2 Cache ECC Check

CPU to DRAM Page Mode

CPU-to-PCI 6 DW FIFO

CPU-to-PCI IDE Posting

CPU-to-PCI Read Buffer

CPU-to-PCI Write Buffer

CPU-to-PCI Write Latency

Chipset Special Features

Concurrent Refresh

DMA n Assigned to

DMA n Used By ISA

DRAM Data Integrity Mode

DRAM ECC/PARITY Select

DRAM Page Idle Timer

DRAM RAS Only Refresh

DRAM RAS# Precharge Time

DRAM Refresh Period

Data Integrity (PAR/ECC)

Daylight Saving

Delay IDE Initial

Delayed Transaction

Drive NA before BRDY

Expansion Board not ready at Slot X

Extended ROM RAM Area

Extended Refresh

Flash BIOS Protection

Floppy Disk Access Control (R/W)

Gate A20 Option

Graphics (AGP) Aperture Size

Hi-Speed Refresh

Hit "Del" Message Display

IRQ n Assigned to

Init AGP Display First

KBC Input Clock

Keyboard/Mouse Power On

MPS 1.4 Support

MPS Version Control For OS

Master Retry Timer

Memory Hole At 15M-16M

Extended ROM RAM Area

Memory Test Tick Sound

Numeric Processor Test

ONB AHA BIOS First

ONB SCSI LVD Term.

ONB SCSI SE Term.

On Board PCI/SCSI BIOS

Onboard AHA BIOS

PCI 2.1 Support

PCI Bus Arbitration

PCI Bus Parking

PCI Clock Frequency

PCI Dynamic Decoding

PCI IRQ Activated by

PCI Latency Timer

PCI Master 0 WS Write

PCI Preempt Timer

PCI/VGA Palette Snoop

PCI master accesses shadow RAM

PCI to ISA Write Buffer

PWRON After PWR-Fail

PWR Button > 4 Secs

PWR Lost Resume State

Passive Release

Password Checking

Peer Concurrency

Power Button Function

Power Management - ACPI

Preempt PCI Master Option

Processor Number Feature

Quick Power On Self Test

RTC Alarm Resume (From Soft)

RTC Y2K H/W Roll Over

Ref/Act Command Delay

Refresh During PCI Cycles

Refresh RAS# Assertion

Report No FDD For WIN 95

Reset Configuration Data

SDRAM Configuration

SYMBIOS (NCR) SCSI BIOS

Security Option

Single ALE Enable

Slow Refresh (1:4)

Spread Spectrum Modulated

Stop CPU at PCI Master

Swap Floppy Drive

Thermal Slow Clock Ratio

Typematic (Rate) Delay (Msec)

Keyboard Reset Control

UART2 Mode Select

USB Keyboard Support Viae

VGA 128k Range Attribute

Video BIOS Cacheable

Video Off Method

Video Off Option

Wait for F1 If Any Error

Weitek Coprocessor

x IR Transmission Delay

x KB Power On Hot Key

x KB Power On Password

x RxD, TxD Active

FDD Controller Failure

8042 Gate-A20 Error!

Floppy disk(s) fail

Hard Disk(s) fail (20)

Hard Disk(s) fail (40)

Hard disk(s) diagnosis fail

HARD DISK INSTALL FAILURE

FLOPPY DISK CNTRLR ERROR OR NO CNTRLR PRESENT

ERROR ENCOUNTERED INITIALIZING HARD DRIVE

ERROR INITIALIZING HARD DRIVE CONTROLLER, HDD Controller Failure

Diskette Boot Failure

DMA #1 Error, DMA #2 Error

DMA Bus Time-out

DISKETTE DRIVES OR TYPES MISMATCH ERROR - RUN SETUP

DISK BOOT FAILURE, INSERT SYSTEM DISK AND PRESS ENTER

DISPLAY SWITCH IS SET INCORRECTLY, Display Switch Not Proper

DISPLAY TYPE HAS CHANGED SINCE LAST BOOT

Cache Memory Bad, Do Not Enable Cache!

CH-2 Timer Error

CMOS Checksum Error, CMOS Checksum Failure

CMOS Memory Size Mismatch

CMOS System Options Not Set

CMOS Time and Date Not Set

CMOS battery failed, CMOS Battery Has Failed, CMOS Battery State Low

BIOS ROM checksum error - System halted

Address Line Short!

Описание настроек BIOS Setup

Drive NA before BRDY

Когда выбрано "Enabled", сигнал NA (читай ниже) устанавливается на один такт раньше последнего сигнала BRDY# в каждом цикле чтения/записи, таким образом вызывая генерацию процессором сигнала ADS# в следующем цикле после BRDY#, устраняя один потерянный цикл. С помощью сигнала BRDY# (Bus Ready) чипсет (точнее, т.н. "северный мост") сообщает процессору о том, что данные доступны для чтения или есть готовность для приема данных для их записи.

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12 июля 2001 года

Используются технологии uCoz